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| K4R271669D Preliminary Direct RDRAMTM 128Mbit RDRAM(D-die) 256K x 16 bit x 32s Banks Direct RDRAMTM Version 1.0 December 2001 Page -1 Version 1.0 Dec. 2001 K4R271669D Change History Version 1.0 ( December 2001 ) - Preliminary * Based on the Rambus RDRAMs for short channel Datasheet 0.97 ver. Preliminary Direct RDRAMTM Page 0 Version 1.0 Dec. 2001 K4R271669D Overview The Rambus Direct RDRAMTM is a general purpose highperformance memory device suitable for use in a broad range of applications including communications, graphics, video, and any other application where high bandwidth and low latency are required. The 128Mbit Direct Rambus DRAMs (RDRAM(R)) are extremely high-speed CMOS DRAMs organized as 8M words by 16. The use of Rambus Signaling Level (RSL) technology permits to 800MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10ns per sixteen bytes). The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM's 32 banks support up to four simultaneous transactions. System oriented features for mobile, graphics and communications include power management, byte masking. Preliminary Direct RDRAMTM SAMSUNG 001 K4R271669D-TCxx Figure 1: Direct RDRAM CSP Package The 128Mbit Direct RDRAMs are offered in a horizontal center-bond fanout CSP. Key Timing Parameters/Part Numbers Speed Organization 256Kx16x32sa Bin I/O Freq. MHz tRAC (Row Access Time) ns Features Highest sustained bandwidth per DRAM device - 1.6GB/s sustained data transfer rate - Separate control and data buses for maximized efficiency - Separate row and column control buses for easy scheduling and highest performance - 32 banks: four transactions can take place simultaneously at full bandwidth data rates Low latency features Part Number -CS8 800 45 K4R271669D-TbCS8 a. "32s" - 32 banks which use a "split" bank architecture. b. "T" - Lead free consumer package. - Write buffer to reduce read latency - 3 precharge mechanisms for controller flexibility - Interleaved transactions Advanced power management: - Multiple low power states allows flexibility in power consumption versus time to transition to active state - Power-down self-refresh Organization: 1Kbyte pages and 32 banks, x 16 - x16 organization for low cost applications Uses Rambus Signaling Level (RSL) for up to 800MHz operation WBGA package(54 Balls) Page 1 Version 1.0 Dec. 2001 K4R271669D Pinouts and Definitions The following table shows the pin assignments of the centerbonded fanout CSP RDRAM package. Table 1: Center-Bonded Fanout CSP Device (Top View) 7 6 5 4 3 2 1 Top View SCK VCMOS NC GND DQA6 DQA3 VDD DQA1 DQA0 GND VREF CTMN GND RQ7 CTM VDD RQ1 RQ4 DQA7 GND CMD DQA4 DQA5 VDD CFM DQA2 GND CFMN VDDA GNDA RQ5 RQ6 VDD RQ3 RQ2 GND Preliminary Direct RDRAMTM DQB0 DQB1 VDD DQB4 DQB5 VDD DQB7 GND SI00 GND DQB2 RQ0 GND DQB6 DQB3 SIO1 VCMOS NC A B C D E F G H J b. Top marking example SAMSUNG 001 K4R271669D-TCxx Top View Chip For consumer package, pin #1(ROW 1, COL A) is located at the A1 position on the top side and the A1 position is marked by the marker " * ". Page 2 Version 1.0 Dec. 2001 K4R271669D Preliminary Direct RDRAMTM Table 2: Pin Description Signal SIO1,SIO0 I/O I/O Type CMOSa CMOSa # Pins center 2 Description Serial input/output. Pins for reading from and writing to the control registers using a serial access protocol. Also used for power management. Command input. Pins used in conjunction with SIO0 and SIO1 for reading from and writing to the control registers. Also used for power management. Serial clock input. Clock source used for reading from and writing to the control registers Supply voltage for the RDRAM core and interface logic. Supply voltage for the RDRAM analog circuitry. Supply voltage for CMOS input/output pins. Ground reference for RDRAM core and interface. Ground reference for RDRAM analog circuitry. Data byte A. Eight pins which carry a byte of read or write data between the Channel and the RDRAM. Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity Logic threshold reference voltage for RSL signals Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. Row access control. Three pins containing control and address information for row accesses. Column access control. Five pins containing control and address information for column accesses. Data byte B.Eight pins which carry a byte of read or write data between the Channel and the RDRAM. No Connection. CMD I 1 SCK I CMOSa 1 VDD VDDa VCMOS GND GNDa DQA7..DQA0 I/O RSLb RSLb RSLb 6 1 2 9 1 8 CFM I 1 CFMN I 1 VREF CTMN I RSL b 1 1 CTM I RSLb RSLb RSLb RSLb 1 RQ7..RQ5 or ROW2..ROW0 RQ4..RQ0 or COL4..COL0 DQB7.. DQB0 NC I 3 I 5 I/O 8 2 54 Total pin count per package a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero. b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero. Page 3 Version 1.0 Dec. 2001 K4R271669D Preliminary Direct RDRAMTM DQB7..DQB0 8 RQ7..RQ5 or ROW2..ROW0 3 CTM CTMN SCK,CMD SIO0,SIO1 CFM CFMN 2 2 RCLK RQ4..RQ0 or COL4..COL0 5 DQA7..DQA0 8 RCLK 1:8 Demux TCLK Packet Decode ROWR ROWA 11 5 5 9 ROP DR BR AV Match 1:8 Demux RCLK Control Registers 6 REFR Power Modes COLX 5 5 Packet Decode COLC 5 5 5 6 C 8 COLM 8 R DEVID XOP DX BX COP DC BC M S Match XOP Decode Match MB MA Mux Row Decode DM Write Buffer Mux Mux PRER ACT Sense Amp 32x64 SAmp SAmp SAmp 1/2 0/1 0 PREX Column Decode & Mask DRAM Core 32x64 512x64x128 Bank 0 Bank 1 Bank 2 *** 32x64 64 SAmp SAmp SAmp 0 0/1 1/2 PREC RD, WR Internal DQB Data Path 64 Internal DQA Data Path 64 64 RCLK 8 8 *** 8 *** 8 RCLK SAmp SAmp SAmp 15 14/15 13/14 Bank 13 Bank 14 Bank 15 SAmp SAmp SAmp 13/14 14/15 15 Write Buffer Write Buffer 1:8 Demux 1:8 Demux 8 8 SAmp SAmp SAmp 16 16/17 17/18 SAmp SAmp SAmp 17/18 16/17 16 Bank 16 Bank 17 Bank 18 *** TCLK 8 8 TCLK *** *** 8:1 Mux 8 8:1 Mux 8 SAmp SAmp SAmp 31 30/31 29/30 Bank 29 Bank 30 Bank 31 Figure 2: 128Mbit(256Kx16x32s) Direct RDRAM Block Diagram SAmp SAmp SAmp 29/30 30/31 31 Page 4 Version 1.0 Dec. 2001 K4R271669D General Description Figure 2 is a block diagram of the 128Mbit Direct RDRAM. It consists of two major blocks: a "core" block built from banks and sense amps similar to those found in other types of DRAM, and a Direct Rambus interface block which permits an external controller to access this core at up to 1.6GB/s. Preliminary Direct RDRAMTM 24-bit ROWA (row-activate) or ROWR (row-operation) packet. COL Pins: The principle use of these five pins is to manage the transfer of data between the DQA/DQB pins and the sense amps of the RDRAM. These pins are de-multiplexed into a 23-bit COLC (column-operation) packet and either a 17-bit COLM (mask) packet or a 17-bit COLX (extended-operation) packet. Control Registers: The CMD, SCK, SIO0, and SIO1 pins appear in the upper center of Figure 2. They are used to write and read a block of control registers. These registers supply the RDRAM configuration information to a controller and they select the operating modes of the device. The nine bit REFR value is used for tracking the last refreshed row. Most importantly, the five bit DEVID specifies the device address of the RDRAM on the Channel. ACT Command: An ACT (activate) command from an ROWA packet causes one of the 512 rows of the selected bank to be loaded to its associated sense amps (two 256 byte sense amps for DQA and two for DQB). PRER Command: A PRER (precharge) command from an ROWR packet causes the selected bank to release its two associated sense amps, permitting a different row in that bank to be activated, or permitting adjacent banks to be activated. Clocking: The CTM and CTMN pins (Clock-To-Master) generate TCLK (Transmit Clock), the internal clock used to transmit read data. The CFM and CFMN pins (Clock-FromMaster) generate RCLK (Receive Clock), the internal clock signal used to receive write data and to receive the ROW and COL pins. RD Command: The RD (read) command causes one of the 64 dualocts of one of the sense amps to be transmitted on the DQA/DQB pins of the Channel. WR Command: The WR (write) command causes a dualoct received from the DQA/DQB data pins of the Channel to be loaded into the write buffer. There is also space in the write buffer for the BC bank address and C column address information. The data in the write buffer is automatically retired (written with optional bytemask) to one of the 64 dualocts of one of the sense amps during a subsequent COP command. A retire can take place during a RD, WR, or NOCOP to another device, or during a WR or NOCOP to the same device. The write buffer will not retire during a RD to the same device. The write buffer reduces the delay needed for the internal DQA/DQB data path turnaround. DQA,DQB Pins: These 18 pins carry read (Q) and write (D) data across the Channel. They are multiplexed/de-multiplexed from/to two 72-bit data paths (running at one-eighth the data frequency) inside the RDRAM. Banks: The 16Mbyte core of the RDRAM is divided into thirty two 0.5Mbyte banks, each organized as 512 rows, with each row containing 64 dualocts, and each dualoct containing 16 bytes. A dualoct is the smallest unit of data that can be addressed. Sense Amps: The RDRAM contains 34 sense amps. Each sense amp consists of 512 bytes of fast storage (256 for DQA and 256 for DQB) and can hold one-half of one row of one bank of the RDRAM. The sense amp may hold any of the 512 half-rows of an associated bank. However, each sense amp is shared between two adjacent banks of the RDRAM (except for sense amps 0, 15, 16, and 31). This introduces the restriction that adjacent banks may not be simultaneously accessed. PREC Precharge: The PREC, RDA and WRA commands are similar to NOCOP, RD and WR, except that a precharge operation is performed at the end of the column operation. These commands provide a second mechanism for performing precharge. PREX Precharge: After a RD command, or after a WR command with no byte masking (M=0), a COLX packet may be used to specify an extended operation (XOP). The most important XOP command is PREX. This command provides a third mechanism for performing precharge. RQ Pins: These pins carry control and address information. They are broken into two groups. RQ7..RQ5 are also called ROW2..ROW0, and are used primarily for controlling row accesses. RQ4..RQ0 are also called COL4..COL0, and are used primarily for controlling column accesses. ROW Pins: The principle use of these three pins is to manage the transfer of data between the banks and the sense amps of the RDRAM. These pins are de-multiplexed into a Page 5 Version 1.0 Dec. 2001 K4R271669D Packet Format Figure 3 shows the formats of the ROWA and ROWR packets on the ROW pins. Table 3 describes the fields which comprise these packets. DR4T and DR4F bits are encoded to contain both the DR4 device address bit and a framing bit which allows the ROWA or ROWR packet to be recognized by the RDRAM. Preliminary Direct RDRAMTM The AV (ROWA/ROWR packet selection) bit distinguishes between the two packet types. Both the ROWA and ROWR packet provide a five bit device address and a five bit bank address. An ROWA packet uses the remaining bits to specify a nine bit row address, and the ROWR packet uses the remaining bits for an eleven bit opcode field. Note the use of the "RsvX" notation to reserve bits for future address field extension. Table 3: Field Description for ROWA Packet and ROWR Packet Field DR4T,DR4F DR3..DR0 BR4..BR0 AV R8..R0 ROP10..ROP0 Description Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit. Device address for ROWA or ROWR packet. Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM. Selects between ROWA packet (AV=1) and ROWR packet (AV=0). Row address for ROWA packet. RsvR denotes bits ignored by the RDRAM. Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions. Figure 3 also shows the formats of the COLC, COLM, and COLX packets on the COL pins. Table 4 describes the fields which comprise these packets. The COLC packet uses the S (Start) bit for framing. A COLM or COLX packet is aligned with this COLC packet, and is also framed by the S bit. The 23 bit COLC packet has a five bit device address, a five bit bank address, a six bit column address, and a four bit opcode. The COLC packet specifies a read or write command, as well as some power management commands. The remaining 17 bits are interpreted as a COLM (M=1) or COLX (M=0) packet. A COLM packet is used for a COLC write command which needs bytemask control. The COLM packet is associated with the COLC packet from at least tRTR earlier. An COLX packet may be used to specify an independent precharge command. It contains a five bit device address, a five bit bank address, and a five bit opcode. The COLX packet may also be used to specify some housekeeping and power management commands. The COLX packet is framed within a COLC packet but is not otherwise associated with any other packet. Table 4: Field Description for COLC Packet, COLM Packet, and COLX Packet Field S DC4..DC0 BC4..BC0 C5..C0 COP3..COP0 M MA7..MA0 MB7..MB0 DX4..DX0 BX4..BX0 XOP4..XOP0 Description Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets. Device address for COLC packet. Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0's). Column address for COLC packet. RsvC denotes bits ignored by the RDRAM. Opcode field for COLC packet. Specifies read, write, precharge, and power management functions. Selects between COLM packet (M=1) and COLX packet (M=0). Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA7..0. Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB7..0. Device address for COLX packet. Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0's). Opcode field for COLX packet. Specifies precharge, IOL control, and power management functions. Page 6 Version 1.0 Dec. 2001 K4R271669D Preliminary Direct RDRAMTM T0 T1 T2 T3 T8 T9 T10 T11 CTM/CFM CTM/CFM ROW2 DR4T DR2 BR0 BR3 RsvR R8 ROW1 ROW0 DR4F DR1 BR1 BR4 RsvR R7 R5 R2 ROW2 DR4T DR2 BR0 BR3 ROW1 ROW0 ROP10 ROP8 ROP5 ROP2 R4 R3 R1 R0 DR4F DR1 BR1 BR4 ROP9 ROP7 ROP4 ROP1 DR3 DR0 BR2 RsvB AV=0 ROP6 ROP3 ROP0 DR3 DR0 BR2 RsvB AV=1 R6 ROWA Packet T0 T1 T2 T3 ROWR Packet T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T12 T13 T14 T15 CTM/CFM DC4 DC3 DC2 COP1 DC1 COP0 DC0 COP2 S=1 RsvC C5 RsvB BC2 BC4 BC1 COP3 BC3 BC0 C4 C3 C2 C1 C0 CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0 ACT a0 PRER c0 COL4 COL3 COL2 COL1 COL0 tPACKET WR b1 MSK (b1) PREX d0 COLC Packet T8 T9 T10 T11 T12 T13 T14 T15 CTM/CFM CTM/CFM COL4 COL3 COL2 COL1 COL0 a S=1a MA7 MA5 MA3 MA1 M=1 MA6 MA4 MA2 MA0 MB7 MB4 MB1 MB6 MB3 MB0 MB5 MB2 COL4 COL3 COL2 COL1 COL0 S=1b DX4 XOP4 RsvB BX1 M=0 DX3 XOP3 BX4 BX0 DX2 XOP2 BX3 DX1 XOP1 BX2 DX0 XOP0 b The The COLM is associated with a previous COLC, and is aligned with the present COLC, indicated by the Start bit (S=1) position. COLM Packet Figure 3: Packet Formats COLX Packet COLX is aligned with the present COLC, indicated by the Start bit (S=1) position. Page 7 Version 1.0 Dec. 2001 K4R271669D Field Encoding Summary Table 5 shows how the six device address bits are decoded for the ROWA and ROWR packets. The DR4T and DR4F encoding merges a fifth device bit with a framing bit. When neither bit is asserted, the device is not selected. Note that a Preliminary Direct RDRAMTM broadcast operation is indicated when both bits are set. Broadcast operation would typically be used for refresh and power management commands. If the device is selected, the DM (DeviceMatch) signal is asserted and an ACT or ROP command is performed. Table 5: Device Field Encodings for ROWA Packet and ROWR Packet DR4T 1 0 1 0 DR4F 1 1 0 0 Device Selection All devices (broadcast) One device selected One device selected No packet present Device Match signal (DM) DM is set to 1 DM is set to 1 if {DEVID4..DEVID0} == {0,DR3..DR0} else DM is set to 0 DM is set to 1 if {DEVID4..DEVID0} == {1,DR3..DR0} else DM is set to 0 DM is set to 0 Table 6 shows the encodings of the remaining fields of the ROWA and ROWR packets. An ROWA packet is specified by asserting the AV bit. This causes the specified row of the specified bank of this device to be loaded into the associated sense amps. An ROWR packet is specified when AV is not asserted. An 11 bit opcode field encodes a command for one of the banks of this device. The PRER command causes a bank and its two associated sense amps to precharge, so another row or an adjacent bank may be activated. The REFA (refresh-activate) command is similar to the ACT command, except the row address comes from an internal register REFR, and REFR is incremented at the largest bank address. The REFP (refresh-precharge) command is identical to a PRER command. The NAPR, NAPRC, PDNR, ATTN, and RLXR commands are used for managing the power dissipation of the RDRAM and are described in more detail in "Power State Management" on page 50. The TCEN and TCAL commands are used to adjust the output driver slew rate and they are described in more detail in "Current and Temperature Control" on page 56. Table 6: ROWA Packet and ROWR Packet Field Encodings ROP10..ROP0 Field DMa 0 1 1 1 1 1 1 1 1 1 1 1 1 AV 10 1 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2:0 --ACT 0 1 0 0 0 0 x x 0 0 0 0 1 1 0 0 0 x x 0 0 0 xc 0 0 0 1 1 x x 0 0 0 x 0 0 1 0 1 x x 0 0 0 x x x x x x 0 1 x x 0 000 000 000 000 000 000 000 000 001 010 000 PRER REFA REFP PDNR NAPR NAPRC ATTNb RLXR TCAL TCEN NOROP No operation. Activate row R8..R0 of bank BR4..BR0 of device and move device to ATTNb. Precharge bank BR4..BR0 of this device. Refresh (activate) row REFR8..REFR0 of bank BR4..BR0 of device. Increment REFR if BR4..BR0 = 11111 (see Figure 51). Precharge bank BR4..BR0 of this device after REFA (see Figure 51). Move this device into the powerdown (PDN) power state (see Figure 48). Move this device into the nap (NAP) power state (see Figure 48). Move this device into the nap (NAP) power state conditionally Move this device into the attention (ATTN) power state (see Figure 46). Move this device into the standby (STBY) power state (see Figure 47). Temperature calibrate this device (see Figure 54). Temperature calibrate/enable this device (see Figure 54). No operation. Name Command Description Row address 1 0 1 x x x x x 0 0 0 1 0 0 x x x x x 0 0 0 0 0 1 0 0 0 x x 0 0 0 a. The DM (Device Match signal) value is determined by the DR4T,DR4F, DR3..DR0 field of the ROWA and ROWR packets. See Table 5. b. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F=1/1). c. An "x" entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP value (011000111000). Page 8 Version 1.0 Dec. 2001 K4R271669D Table 7 shows the COP field encoding. The device must be in the ATTN power state in order to receive COLC packets. The COLC packet is used primarily to specify RD (read) and WR (write) commands. Retire operations (moving data from the write buffer to a sense amp) happen automatically. See Figure 18 for a more detailed description. Preliminary Direct RDRAMTM The COLC packet can also specify a PREC command, which precharges a bank and its associated sense amps. The RDA/WRA commands are equivalent to combining RD/WR with a PREC. RLXC (relax) performs a power mode transition. See "Power State Management" on page 50. Table 7: COLC Packet Field Encodings S DC4.. DC0 (select device)a ---/= (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) COP3..0 Name --------x000b x001 x010 x011 x100 x101 x110 x111 1xxx NOCOP WR RSRV RD PREC WRA RSRV RDA RLXC Command Description No operation. Retire write buffer of this device. Retire write buffer of this device. Retire write buffer of this device, then write column C5..C0 of bank BC4..BC0 to write buffer. Reserved, no operation. Read column C5..C0 of bank BC4..BC0 of this device. Retire write buffer of this device, then precharge bank BC4..BC0 (see Figure 15). Same as WR, but precharge bank BC4..BC0 after write buffer (with new data) is retired. Reserved, no operation. Same as RD, but precharge bank BC4..BC0 afterward. Move this device into the standby (STBY) power state (see Figur e 47). 0 1 1 1 1 1 1 1 1 1 1 a. "/=" means not equal, "==" means equal. b. An "x" entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value (1001). Table 8 shows the COLM and COLX field encodings. The M bit is asserted to specify a COLM packet with two 8 bit bytemask fields MA and MB. If the M bit is not asserted, an COLX is specified. It has device and bank address fields, and an opcode field. The primary use of the COLX packet is to permit an independent PREX (precharge) command to be specified without consuming control bandwidth on the ROW pins. It is also used for the CAL(calibrate) and SAM (sample) current control commands (see "Current and Temperature Control" on page 56), and for the RLXX power mode command (see "Power State Management" on page 50). Table 8: COLM Packet and COLX Packet Field Encodings M 1 0 0 0 0 0 0 0 DX4 .. DX0 (selects device) ---/= (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) XOP4..0 00000 1xxx0a x10x0 x11x0 xxx10 xxxx1 Name MSK NOXOP PREX CAL CAL/SAM RLXX RSRV Command Description MB/MA bytemasks used by WR/WRA. No operation. No operation. Precharge bank BX4..BX0 of this device (see Figure 15). Calibrate (drive) IOL current for this device (see Figure 53). Calibrate (drive) and Sample ( update) IOL current for this device (see Figure 53). Move this device into the standby (STBY) power state (see Figur e 47). Reserved, no operation. a. An "x" entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010). Page 9 Version 1.0 Dec. 2001 K4R271669D Electrical Conditions Table 9: Electrical Conditions Symbol TJ VDD, VDDA VDD,N, VDDA,N vDD,N, vDDA,N VCMOSa VREF VDIL VDIH VDIS RDA VCM VCIS,CTM VCIS,CFM VIL,CMOS VIH,CMOS Preliminary Direct RDRAMTM Parameter and Conditions Junction temperature under bias Supply voltage Supply voltage droop (DC) during NAP interval (t Supply voltage ripple (AC) during NAP interval (t Supply voltage for CMOS pins (2.5V controllers) Supply voltage for CMOS pins (1.8V controllers) Reference voltage RSL data input - low voltage RSL data input - high voltageb NLIMIT) NLIMIT) Min 2.50 - 0.13 -2.0 VDD 1.80 - 0.1 1.40- 0.2 VREF - 0.5 VREF + 0.2 0.4 0.67 1.3 0.35 0.225 0.3c Max 95 2.50 + 0.25 2.0 2.0 VDD 1.80 + 0.2 1.40 + 0.2 VREF - 0.2 VREF + 0.5 1.0 1.00 1.8 1.00 1.00 VCMOS/2 - 0.25 VCMOS+0.3d Unit C V % % V V V V V V V V V V V RSL data input swing: VDIS = VDIH - VDIL RSL data asymmetry: RDA = (VDIH - VREF) / (VREF - VDIL) RSL clock input - common mode VCM = (VCIH+VCIL)/2 RSL clock input swing: VCIS = VCIH - VCIL (CTM,CTMN pins). RSL clock input swing: VCIS = VCIH - VCIL (CFM,CFMN pins). CMOS input low voltage CMOS input high voltage VCMOS/2 + 0.25 a. VCMOS must remain on as long as VDD is applied and cannot be turned off. b. VDIH is typically equal to V TERM (1.8V0.1V) under DC conditions in a system. c. Voltage undershoot is limited to -0.7V for a duration of less than 5ns. d. Voltage overshoot is limited toVCMOS +0.7V for a duration of less than 5ns. Page 10 Version 1.0 Dec. 2001 K4R271669D Electrical Characteristics Table 10: Electrical Characteristics Symbol JC IREF IOH IALL IOL rOUT IOL II,CMOS VOL,CMOS VOH,CMOS Parameter and Conditions Junction-to-Case thermal resistance VREF current @ VREF,MAX RSL output high current @ (0VOUTVDD) RSL IOL current @ VOL = 0.9V, RSL IOL current resolution step Dynamic output impedance @ VOL= 0.9V RSL IOL current @ VOL = 1.0V b,c Preliminary Direct RDRAMTM Min -10 -10 30.0 150 26.6 -10.0 VCMOS-0.3 Max 0.5 10 10 90.0 2.0 30.6 10.0 0.3 - Unit C/Watt A A mA mA mA A V V VDD,MIN , TJ,MAXa CMOS input leakage current @ (0VI,CMOSVCMOS) CMOS output voltage @ IOL,CMOS= 1.0mA CMOS output high voltage @ IOH,CMOS = -0.25mA a. This measurement is made in manual current control mode; i.e. with all output device legs sinking current. b. This measurement is made in automatic current control mode after at least 64 current control calibration operations to a device and after CCA and CCB are initialized to a value of 64. This value applies to all DQA and DQB pins. c. This measurement is made in automatic current control mode in a 25 test system with VTERM= 1.714V and VREF= 1.357V and with the ASYMA and ASYMB register fields set to 0. Page 11 Version 1.0 Dec. 2001 K4R271669D Timing Conditions Table 11: Timing Conditions Symbol tCYCLE tCR, tCF tCH, tCL tTR tDCW tDR, tDF tS, tH tDR1, tDF1 tDR2, tDF2 tCYCLE1 Preliminary Direct RDRAMTM Parameter CTM and CFM cycle times (-800) CTM and CFM input rise and fall times. Use the minimum value of these parameters during testing. CTM and CFM high and low times CTM-CFM differential (MSE/MS=0/0) CTM-CFM differential (MSE/MS=1/1) a Domain crossing window DQA/DQB/ROW/COL input rise/fall times (20% to 80%). Use the minimum value of these parameters during testing. DQA/DQB/ROW/COL-to-CFM setup/hold @ t CYCLE=2.50 SIO0, SIO1 input rise and fall times CMD, SCK input rise and fall times SCK cycle time - Serial control register transactions SCK cycle time - Power transitions Min 2.50 0.2 Max 3.83 0.5 Unit ns ns Figure(s) Figure 55 Figure 55 40% 0.0 0.9 -0.1 0.2 0.250b 1000 10 4.25 1.25 1 40 40 0 5.5 -1 5 4 12 8 2 100 7 60% 1.0 1.0 0.1 0.65 tCYCLE tCYCLE tCYCLE ns Figure 55 Figure 43 Figure 55 Figure 61 Figure 56 5.0 2.0 10.0 32 200 ns ns ns ns ns ns ns ns ns ns ns ns tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE s ms s Figure 56 Figure 58 Figure 58 Figure 58 Figure 58 Figure 58 Figure 58 Figure 58 Figure 58 Figure 58 Figure 49 Figure 59 Figure 49 Figure 49 Figure 48 Figure 53 Figure 53 Figure 49 Figure 48 Figure 47 Figure 46 Figure 51 Figure 52 tCH1, tCL1 tS1 tH1 tS2 tH2 tS3 tH3 tS4 tH4 tNPQ tREADTOCC tCCSAMTOREAD tCE tCD tFRM tNLIMIT tREF tBURST SCK high and low times CMD setup time to SCK rising or falling edgec CMD hold time to SCK rising or falling edgec SIO0 setup time to SCK falling edge SIO0 hold time to SCK falling edge PDEV setup time on DQA5..0 to SCK rising edge. PDEV hold time on DQA5..0 to SCK rising edge. ROW2..0, COL4..0 setup time for quiet window ROW2..0, COL4..0 hold time for quiet window d Quiet on ROW/COL bits during NAP/PDN entry Offset between read data and CC packets (same device) Offset between CC packet and read data (same device) CTM/CFM stable before NAP/PDN exit CTM/CFM stable after NAP/PDN entry ROW packet to COL packet ATTN framing delay Maximum time in NAP mode Refresh interval Interval after PDN or NAP (with self-refresh) exit in which all banks of the RDRAM must be refreshed at least once. Page 12 Version 1.0 Dec. 2001 K4R271669D Table 11: Timing Conditions Symbol tCCTRL tTEMP tTCEN tTCAL tTCQUIET tPAUSE Preliminary Direct RDRAMTM Parameter Current control interval Min 34 tCYCLE Max 100ms Unit ms/tCYCLE Figure(s) Figure 53 Temperature control interval TCE command to TCAL command TCAL command to quiet window Quiet window (no read data) RDRAM delay (no RSL operations allowed) 150 2 140 100 2 200.0 ms tCYCLE tCYCLE tCYCLE s Figure 54 Figure 54 Figure 54 Figure 54 page 38 a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0. b. tS,MIN and tH,MIN for other tCYCLE values can be interpolated between or extrapolated from the timings at the 3 specified tCYCLE values. c. With VIL,CMOS =0.5VCMOS-0.4V and VIH,CMOS=0.5VCMOS+0.4V d. Effective hold becomes tH4'=t H4+[PDNXA*64*tSCYCLE+tPDNXB,MAX]-[PDNX*256*tSCYCLE] if [PDNX*256*tSCYCLE] < [PDNXA*64*tSCYCLE+tPDNXB,MAX]. See Figure 49. Page 13 Version 1.0 Dec. 2001 K4R271669D Timing Characteristics Table 12: Timing Characteristics Symbol tQ tQR, tQF tQ1 tHR tQR1, tQF1 tPROP1 tNAPXA tNAPXB tPDNXA tPDNXB tAS tSA tASN tASP Parameter CTM-to-DQA/DQB output time @ tCYCLE=2.50ns DQA/DQB output rise and fall times SCK(neg)-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read data valid). SCK(pos)-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read data hold). SIOOUT rise/fall @ C LOAD,MAX = 20pF SIO0-to-SIO1 or SIO1-to-SIO0 delay @ CLOAD,MAX = 20pF NAP exit delay - phase A NAP exit delay - phase B PDN exit delay - phase A PDN exit delay - phase B ATTN-to-STBY power state delay STBY-to-ATTN power state delay ATTN/STBY-to-NAP power state delay ATTN/STBY-to-PDN power state delay Min -0.310 0.2 2 - Preliminary Direct RDRAMTM Max +0.310 0.45 10 5 10 50 40 4 9000 1 0 8 8 Unit ns ns ns ns ns ns ns ns s tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE Figure(s) Figure 57 Figure 57 Figure 60 Figure 60 Figure 60 Figure 60 Figure 49 Figure 49 Figure 49 Figure 49 Figure 47 Figure 47 Figure 48 Figure 48 Page 14 Version 1.0 Dec. 2001 K4R271669D Timing Parameters Table 13: Timing Parameter Summary Parameter Description Min -45 -800 28 20 8 Preliminary Direct RDRAMTM Max Units Figure(s) tRC tRAS tRP Row Cycle time of RDRAM banks -the interval between ROWA packets with ACT commands to the same bank. RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT command and next ROWR packet with PRER a command to the same bank. Row Precharge time of RDRAM banks - the interval between ROWR packet with PRER a command and next ROWA packet with ACT command to the same bank. Precharge-to-precharge time of RDRAM device - the interval between successive ROWR packets with PRER a commands to any banks of the same device. RAS-to-RAS time of RDRAM device - the interval between successive ROWA packets with ACT commands to any banks of the same device. RAS-to-CAS Delay - the interval from ROWA packet with ACT command to COLC packet with RD or WR command). Note - the RAS-to-CAS delay seen by the RDRAM core (tRCD-C) is equal to t RCD-C = 1 + tRCD because of differences in the row and column paths through the RDRAM interface. CAS Access delay - the interval from RD command to Q read data. The equation for tCAC is given in the TPARM register in Figure 40. CAS Write Delay (interval from WR command to D write data. CAS-to-CAS time of RDRAM bank - the interval between successive COLC commands). Length of ROWA, ROWR, COLC, COLM or COLX packet. Interval from COLC packet with WR command to COLC packet which causes retire, and to COLM packet with bytemask. The interval (offset) from COLC packet with RDA command, or from COLC packet with retire command (after WRA automatic precharge), or from COLC packet with PREC command, or from COLX packet with PREX command to the equivalent ROWR packet with PRER. The equation for tOFFP is given in the TPARM register in Figure 40. Interval from last COLC packet with RD command to ROWR packet with PRER. Interval from last COLC packet with automatic retire command to ROWR packet with PRER. 64sb - tCYCLE tCYCLE tCYCLE Figure 16 Figure 17 Figure 16 Figure 17 Figure 16 Figure 17 Figure 13 Figure 14 Figure 16 Figure 17 tPP tRR tRCD 8 8 9 - tCYCLE tCYCLE tCYCLE tCAC tCWD tCC tPACKET tRTR tOFFP 8 6 4 4 8 4 12 6 4 4 tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE Figure 5 Figure 40 Figure 5 Figure 16 Figure 17 Figure 3 Figure 18 Figure 15 Figure 40 tRDP tRTP 4 4 - tCYCLE tCYCLE Figure 16 Figure 17 a. Or equivalent PREC or PREX command. See Figure 15. b. This is a constraint imposed by the core, and is therefore in units of s rather than tCYCLE. Page 15 Version 1.0 Dec. 2001 K4R271669D Absolute Maximum Ratings Table 14: Absolute Maximum Ratings Symbol VI,ABS VDD,ABS, VDDA,ABS TSTORE Preliminary Direct RDRAMTM Parameter Voltage applied to any RSL or CMOS pin with respect to Gnd Voltage on VDD and VDDA with respect to Gnd Storage temperature Min - 0.3 - 0.5 - 50 Max VDD+0.3 VDD+1.0 100 Unit V V C IDD - Supply Current Profile Table 15: Supply Current Profile Min I DD value RDRAM Power State and Steady-State Transaction Ratesa Max -45 -800 5000 4 75 Unit IDD,PDN IDD,NAP IDD,STBY IDD,REFRESH IDD,ATTN IDD,ATTN-W IDD,ATTN-R Device in PDN, self-refresh enabled and INIT.LSR=0. Device in NAP. Device in STBY. This is the average for a device in STBY with (1) no packets on the Channel, and (2) with packets sent to other devices. Device in STBY and refreshing rows at the tREF,MAX period. Device in ATTN. This is the average for a device in ATTN with (1) no packets on the Channel, and (2) with packets sent to other devices. Device in ATTN. ACT command every 8*t CYCLE, PRE command every 8*tCYCLE, WR command every 4*tCYCLE, and data is 1100..1100 Device in ATTN. ACT command every 8*t CYCLE, PRE command every 8*tCYCLE, RD command every 4*tCYCLE, and data is 1111..1111b - A mA mA - 75 115 mA mA - 500 mA - 480 mA a. CMOS interface consumes power in all power states. b. This does not include the IOL sink current. The RDRAM dissipates IOL*VOL in each output driver when a logic one is driven. Table 16: Supply Current at Initialization Symbol IDD,PWRUP,D IDD,SETR,D Parameter IDD from power -on to SETR IDD from SETR to CLRR Allowed Range of t CYCLE 3.33ns to 3.83ns 2.50ns to 3.32ns 3.33ns to 3.83ns 2.50ns to 3.32ns VDD VDD,MIN VDD,MIN Min - Max 150a 200 250 332 Unit mA - mA a.The supply current will be 150mA when tCYCLE is in the range 15ns to 1000ns. Page 16 Version 1.0 Dec. 2001 K4R271669D Capacitance and Inductance Table 17: RSL Pin Parasitics Symbol LI L12 Parameter and Conditions - RSL pins RSL effective input inductance Mutual inductance between any DQA or DQB RSL signals Mutual inductance between any ROW or COL RSL signals LI CI C12 CI RI Difference in LI value between any RSL pins of a single device. RSL effective input capacitance a Mutual capacitance between any RSL signals. Difference in C I value between average of {CTM, CTMN, CFM, CFMN} and any RSL pins of a single device RSL effective input resistance 4 2.0 Min Preliminary Direct RDRAMTM Max 4.0 0.6 0.6 2.0 2.6 0.2 0.12 Unit nH nH Figure Figure 62 Figure 62 nH pF pF pF Figure 62 Figure 62 Figure 62 Figure 62 18 Figure 62 a. This value is a combination of the device IO circuitry and package capacitances measured at VDD=2.5V and f=400MHz with pin biased at 1.4V. Table 18: CMOS Pin Parasitics Symbol LI ,CMOS CI ,CMOS CI ,CMOS,SIO Parameter and Conditions - CMOS pins CMOS effective input inductance CMOS effective input capacitance (SCK,CMD) CMOS effective input capacitance (SIO1, a Min Max 8.0 Unit nH pF pF Figure Figure 62 1.7 - 2.1 7.0 SIO0)a a. This value is a combination of the device IO circuitry and package capacitances. Page 17 Version 1.0 Dec. 2001 K4R271669D Center-Bonded Fanout Package (54 Balls) Figure 4 shows the form and dimensions of the recommended package for the center-bonded Fanout CSP device class. D A 1 2 3 4 5 e2 6 7 A B C D E F G H J Bottom Bottom Preliminary Direct RDRAMTM Top d E1 e1 Bottom E Figure 4: Center-Bonded Fanout CSP Package Table 19 lists the numerical values corresponding to dimensions shown in Figure 4 Table 19: Center-Bonded Fanout CSP Package Dimension Symbol e1 e2 A D E E1 d Parameter Ball pitch (x-axis) Ball pitch (y-axis) Package body length Package body width Package total thickness Ball height Ball diameter Min 1.27 1.27 11.9 11.7 0.45 0.55 Max 1.27 1.27 12.1 11.9 1.25 0.55 0.65 Unit mm mm mm mm mm mm mm Page 18 Version 1.0 Dec. 2001 |
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